Workshop "Code Optimization for Next Generation Intel Processors"

Speedup Your Code on Next Generation Intel® Xeon Phi™ and Xeon™ Processors at HLRN

The next generation of Intel® Xeon Phi™ processors - code named Knights Landing (KNL) - is available as stand-alone CPU and features up to 72 cores, an increased single-core performance, integration of high-bandwidth memory, and different device partition models. The recently upgraded Cray TDS at ZIB - being part of the HLRN complex 'Konrad' - now features 80 KNL nodes and is open for the HLRN community for code evaluation, optimization and benchmarking.

Existing codes need to be modernized to take full advantage of the architectural features of today's Intel® Xeon Phi™ and near-future Intel® Xeon™ processors. Newly developed code should be designed to do so from the beginning.

We invite all HLRN code developers and many-core enthusiasts to a 2-day workshop on code optimization for KNL and tomorrow's multi- and many-core processors.

DATE: Monday, Sept 26, 2016, 10am - Tuesday, Sept 27, 2016, 6pm

LOCATION: Berlin, Zuse Institute Berlin (ZIB), Lecture Hall and Seminar Room, (Eingang Foyer Rundbau)

REGISTRATION & TRAVEL INFORMATION: Please use the Registration Page which provides information about the location of the Zuse Institute in Berlin.

Prerequisites and Additional Information

  • Please bring your own laptop for the practical sessions.
    • The laptop needs to have WLAN support.
    • For attendees without a HLRN account we provide temporary accounts. Please have a tool ready for private/public key generation.
    • A ssh client should be installed on you laptop for login into the HLRN system. For Windows we recommend MobaXterm.
    • To use the GUIs of various tools your laptop OS should have a support for X11 compatible client connections. For Windows, MobaXterm comes with a X11 server.
  • Do not forget to bring your own code for Day 2.
  • For lunch we made a reservation for all attendees in the esskultur Dahlem. Please note that you have to pay for yourself. The food offerings cost between 4 and 10 EUR.

Material

Agenda

DAY 1: Mon, Sep. 26, 2016
09:30 - 10:00 Registration
10:00 - 10:15 Opening (Th. Steinke, ZIB)
10:15 - 11:00 The Intel Xeon Phi Processor Architecture (Codename "Knights Landing") (G. Zitzlsberger, Intel)
11:00 - 11:10 Break
11:10 - 11:30 Vectorization for KNL with the Intel Compiler and OpenMP 4.x (G. Zitzlsberger, Intel)
11:30 - 12:00 Portable SIMD Programming (F. Wende, ZIB)
12:00 - 12:25 The Roofline Model (M. Noack, ZIB)
12:45 - 13:45 Lunch
13:45 - 14:10 The Intel Vector Advisor (K.-D. Oertel, Intel)
14:10 - 14:30 Usage Models of MCDRAM (G. Zitzlsberger, Intel)
14:30 - 15:15 Which Tool Should I Use? (K.-D. Oertel, Intel)
15:15 - 15:25 Break
15:25 - 15:40 Teaser Talks: KART, LIBFFT, Cross-Compiler Performance, BQCD, libxsmm (M. Noack, F. Wende, Th. Schütt, ZIB and G. Zitzlsberger, Intel)
15:40 - 16:10 KNL Support by Cray Compiler (J. Thorbecke, Cray)
16:10 - 16:55 Cray Performance Analysis Tools for KNL (H. Poxon, Cray)
  Cray PAT Demo (H.-H. Frese, ZIB)
16:55 - 17:40 Using the KNL on Cray XC: MPI, Process & Thread Placement (J. Thorbecke, Cray)
17:40 - 18:00 Preparation for Day 2: SSH Key Upload, TDS Login (H.-H. Frese, ZIB)
18:00 Wrap-up Day 1
   
DAY 2: Tue, Sep. 27, 2016
08:30 - 09:00 Registration
09:00 - 09:20 Access to the Cray TDS (H.-H. Frese, ZIB), TDS Short Usage Guide
09:20 - 11:00 Hackathon / Hands-on Session
11:00 - 11:15 Break
11:15 - 12:45 Hackathon / Hands-on Session (cont.)
12:45 - 13:45 Lunch
13:45 - 15:15 Hackathon / Hands-on Session (cont.)
15:15 - 15:30 Break
15:30 - 17:45 Hackathon / Hands-on Session (cont.)
18:00 Wrap-up Day 2


Created by ThomasSteinke - 21 Sep 2016

Letzte Änderung: WolfgangBaumann - 2017-01-24 11:24 (UTC)(Version: 12)

 
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